Scaling of the transistors is the driving force for the IC technology which extends Moore’s law providing performance enhancement and increased device density.
A. Scaling of Planar MOSFET
The number of transistors per chip and the device performance has been improving exponentially over the last three decades. As the channel length is reduced, the performance improves, the power per switching event decreases, improves the drive current and device density 30. Scaling is driven by decreasing the channel length along with decrease in gate oxide thickness to increase the current drive of the transistor. However, increased electric field is encountered by this scaling. The demand for high performance and integration of transistors has accelerated the scaling trends in almost every critical parameter, such as lithography, effective channel length, gate dielectric thickness, supply voltage, device leakage, etc. Some of these parameters are approaching fundamental limits enabling alternatives to the existing material and exploration of new device structures in order to continue scaling 30.
B. Showstoppers of Planar CMOS Scaling
Recent unfavorable effects introduced by the scaling have become very prominent. First, the power density increases. Secondly, increase in interconnect delay, current density, and noise. Device parasitic resistance impacts the circuit performance by reducing the current drive and thus increases delay 22. Lastly, since the number of devices on a chip increases, the design and the testing becomes more difficult and time consuming. Main show stoppers for CMOS scaling are:
· Increase on off-state current and parasitic currents like gate tunneling current, Direct Source-Drain tunneling which increases the static power of the devices.
· Increase in parasitic capacitance, which increases the dynamic power of the devices.
· Short Channel Effects (SCE) results in Drain Induced Barrier Lowering (DIBL), Hot carrier effects, Direct Source drain tunneling etc.
· Drain Induced Barrier Lowering (DIBL)- Depletion region of source and drain can extend into the channel even without bias, as the channel length decreases. This phenomenon in which the source and drain in effect take part of channel charge, which would otherwise be controlled by the gate is known as charge sharing. Increase in drain bias increases the drain depletion region, and interacts with the source to channel junction and hence lowers the potential barrier. This is known as Drain Induced Barrier Lowering (DIBL). As a result of this reduced source junction barrier enables electrons get easily injected into the channel and the gate voltage loses its control over the drain current 28.
· Hot carrier effect- The field in the reversed bias drain junction can lead to impact ionization and carrier multiplication. The resulting holes contribute to substrate current and some may move to the source, where they lower source barrier and result in electron injected from source into p-region. Another hot carrier effect causes the electrons to tunnel through the barrier into oxide, where they get trapped in the oxide, thereby changing the threshold voltage and I-V characteristics of the device 28.
· Gate tunneling current- As the MOSFET is scaled, the gate oxide thickness is also reduced as per scaling rule. The ultra-thin gate oxide appreciates direct carrier tunneling from gate to channel.
· Direct Source-Drain tunneling causes significant amount of carriers tunnel directly from source to drain through the barrier potential 3.
· Lithography Challenges-Photolithography is an issue with continuous scaling. These are the results of incompetency of lithography-based techniques to provide the resolution below the wavelength of the light to manufacture CMOS devices 6. Extreme Ultra-violet (EUV) lithography has not yet arrived in industry yet 9.
· Interconnect Delays-As the MOSFETs become smaller and faster, the interconnection delays on integrated circuit become increasingly important. Both the resistance of the metal lines and the capacitance between them go up resulting in unacceptable RC delays. The signal integrity is becoming one of the major design issues due to the increased coupling capacitance between interconnects.